Countercomputing Manifesto
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Said standard shall encompass both hardware and software, and shall be implementable in real hardware by using only currently produced, off the shelf parts, and services from such third party companies as needed to manufacture quality printed circuit boards and other hardware.
In terms of hardware performance, the standard shall mandate minimums, but restrict no maximums. It chooses each component based on practical need, performance, and accessibility to the hobbyist market.
The guiding principle of the standard is to make the best use of existing, commercially available parts to allow for the construction of a practical computer which exists to serve the needs and desires of the owner, without regard to what benefit or value might be extracted by some unknown third party.
Performance relative to common "PC" hardware is not a factor in this standard; nor is compatibility with existing modern software. Compatibility with modern hardware is considered on a case-by-case basis, and only when doing so is the most practical and effective option.
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The guiding principle of the standard is to make the best use of existing, commercially available parts to allow for the construction of a practical computer which exists to serve the needs and desires of the owner, without regard to what benefit or value might be extracted by some unknown third party.
Performance relative to common "PC" hardware is not a factor in this standard; nor is compatibility with existing modern software. Compatibility with modern hardware is considered on a case-by-case basis, and only when doing so is the most practical and effective option.
From schematics to source code, all parts of a standard-compliant design shall be made available to the owner of the device under terms which do not restrict or compel the use to which the device or software may be put, nor restrict the rights to distribute and extend the machine.
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From schematics to source code, all parts of a standard-compliant design shall be made available to the owner of the device under terms which do not restrict or compel the use to which the device or software may be put, nor restrict the rights to distribute and extend the machine.
The machine created by this standard is intended for use by a user familiar with software and hardware development, or at least interested in learning to do so.
The standard is divided into levels:
Level Zero is the simplest system. It mandates a minimum viable system capable of editing and consuming text, building new software from source code, and using software made by others.
Level One is a more complete system, with mandated and standardized interfaces to networking and graphics hardware.
Level Two is aspirational -- it mandates a new operating system and software stack, designed from the ground up to support the hardware design as it has matured.
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The machine created by this standard is intended for use by a user familiar with software and hardware development, or at least interested in learning to do so.
The standard is divided into levels:
Level Zero is the simplest system. It mandates a minimum viable system capable of editing and consuming text, building new software from source code, and using software made by others.
Level One is a more complete system, with mandated and standardized interfaces to networking and graphics hardware.
Level Two is aspirational -- it mandates a new operating system and software stack, designed from the ground up to support the hardware design as it has matured.
Obviously, any computer needs a CPU. The choice of CPU architecture in a context such as this is limited by several factors:
- Availability: The CPU must be available to all commercially
- Simplicity: The CPU must be simple enough to be understood by a single person
- Openness: The CPU must be of a design which exposes the full system bus, and not restrict the design of a system built around it. This disqualifies all "system-on-chip" type designs.
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Obviously, any computer needs a CPU. The choice of CPU architecture in a context such as this is limited by several factors:
- Availability: The CPU must be available to all commercially
- Simplicity: The CPU must be simple enough to be understood by a single person
- Openness: The CPU must be of a design which exposes the full system bus, and not restrict the design of a system built around it. This disqualifies all "system-on-chip" type designs.
CPU performance is only a factor in as much as two otherwise fitting CPUs should be compared for performance. Performance relative to disqualified CPUs is not a factor.
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CPU performance is only a factor in as much as two otherwise fitting CPUs should be compared for performance. Performance relative to disqualified CPUs is not a factor.
A survey of available CPUs which fit the requirements:
- Z80 family (Z80, Z180, eZ80)
- 6502 family (65C02, 65C816)
- RISC-V (potentially)
The Z80 family has several in-production chips, all of which meet the requirements.
The 6502 family has four in-production chips, two of which are effectively systems-on-chip that expose the full system bus.
There is no current RISC-V CPU which meets the requirements, but as it is an open architecture, it is certainly possible for someone to design and implement one.
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A survey of available CPUs which fit the requirements:
- Z80 family (Z80, Z180, eZ80)
- 6502 family (65C02, 65C816)
- RISC-V (potentially)
The Z80 family has several in-production chips, all of which meet the requirements.
The 6502 family has four in-production chips, two of which are effectively systems-on-chip that expose the full system bus.
There is no current RISC-V CPU which meets the requirements, but as it is an open architecture, it is certainly possible for someone to design and implement one.
The x86 family of CPUs would certainly simplify some things, however the complexity of the support hardware makes this problematic at best.
PowerPC and ARM are both fine choices, except that they are not commonly available as discrete CPUs that expose the full bus.
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The x86 family of CPUs would certainly simplify some things, however the complexity of the support hardware makes this problematic at best.
PowerPC and ARM are both fine choices, except that they are not commonly available as discrete CPUs that expose the full bus.
The author knows little of the Loongson architecture, other than it is a descendant of MIPS. It is not commercially available to the users as far as the author knows.
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The author knows little of the Loongson architecture, other than it is a descendant of MIPS. It is not commercially available to the users as far as the author knows.
Thus, it is clear that the choice of CPU architecture comes down to either Z80 family or 6502 family.
The fastest Z80 chip is the eZ80, which can be had rated up to 50MHz, and is a pipelined design, which performs more or less three times as fast per MHz than a standard Z80 -- so a 50MHz eZ80 performs more or less like a 150MHz Z80.
The fastest 6502 family chip is the 65C816, which can be had rated at 14MHz, and commonly overclocks up to 20MHz.
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A survey of available CPUs which fit the requirements:
- Z80 family (Z80, Z180, eZ80)
- 6502 family (65C02, 65C816)
- RISC-V (potentially)
The Z80 family has several in-production chips, all of which meet the requirements.
The 6502 family has four in-production chips, two of which are effectively systems-on-chip that expose the full system bus.
There is no current RISC-V CPU which meets the requirements, but as it is an open architecture, it is certainly possible for someone to design and implement one.
@mos_8502 What if you focused on some kind of virtual architecture? Something like, for example WebAssembly (just using it as an example, not an endorsement), then your hardware platform could change and evolve as needed as different CPUs become available, or stop being available? Were this to be a reasonable option, the virtual architecture would have to be simple enough such that a VM for it could fairly trivially be implemented on this set of 8 bit CPUs
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Obviously, any computer needs a CPU. The choice of CPU architecture in a context such as this is limited by several factors:
- Availability: The CPU must be available to all commercially
- Simplicity: The CPU must be simple enough to be understood by a single person
- Openness: The CPU must be of a design which exposes the full system bus, and not restrict the design of a system built around it. This disqualifies all "system-on-chip" type designs.
@mos_8502 love this thread, thank you for thinking through this and writing it out. i was wondering if you could explain the reasoning of "openness" requirement a bit more? why is it important that the full bus is exposed? (not challenging the idea, just interested to learn more about your specific reasoning)
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@mos_8502 love this thread, thank you for thinking through this and writing it out. i was wondering if you could explain the reasoning of "openness" requirement a bit more? why is it important that the full bus is exposed? (not challenging the idea, just interested to learn more about your specific reasoning)
@aparrish Designing a system around, say, an RPI SoC restricts a lot of choices, and binds closely to whatever hardware is on the SoC chosen. This is a problem because SoCs have a very short in-production life. Exposing the full system bus allows for replacing hardware components as things leave production status.
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Thus, it is clear that the choice of CPU architecture comes down to either Z80 family or 6502 family.
The fastest Z80 chip is the eZ80, which can be had rated up to 50MHz, and is a pipelined design, which performs more or less three times as fast per MHz than a standard Z80 -- so a 50MHz eZ80 performs more or less like a 150MHz Z80.
The fastest 6502 family chip is the 65C816, which can be had rated at 14MHz, and commonly overclocks up to 20MHz.
While the eZ80 at 50MHz obviously outperforms the 65C816 at 14MHz, the eZ80 is a large surface-mount package, while the '816 is a simple DIP. For the hobbyist, this is also a factor. However, in the modern age, it is simple to have a breakout module or carrier board made which puts the eZ80 on a pin grid array, for example.
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While the eZ80 at 50MHz obviously outperforms the 65C816 at 14MHz, the eZ80 is a large surface-mount package, while the '816 is a simple DIP. For the hobbyist, this is also a factor. However, in the modern age, it is simple to have a breakout module or carrier board made which puts the eZ80 on a pin grid array, for example.
At least initially, having software tools to run on a new system is preferable. There exists no OS we could simply pick up and use for the 65816. The eZ80 is supported by ROMWBW, which provides a fairly complete implementation of CP/M to run on the eZ80.
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At least initially, having software tools to run on a new system is preferable. There exists no OS we could simply pick up and use for the 65816. The eZ80 is supported by ROMWBW, which provides a fairly complete implementation of CP/M to run on the eZ80.
Then again, there is an excellent cross-compiler for the 65816 arch (Calypsi), which might make developing an OS easier.
All of this is moot, of course, if there turns out to be a better option for CPU.
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At least initially, having software tools to run on a new system is preferable. There exists no OS we could simply pick up and use for the 65816. The eZ80 is supported by ROMWBW, which provides a fairly complete implementation of CP/M to run on the eZ80.
@mos_8502
As long as you provide simple IO routines, you can run C64/PET BASIC on the 6502. The C64 kernel has actually quite a nice operating system API even though it's single threaded and lacks in memory management. Itball comes down to providing IO drivers -
Countercomputing Manifesto
Draft 0.0.1
For decades, computing power has been steadily growing, without a commensurate boost in the utility to the user. In fact, this increase in power has largely been used against the user -- extracting value from the user, at little or no benefit to the user, primarily for the benefit of corporations who produce and sell nothing of real utility themselves.
We assert that the sole agency over the use and output of privately owned tools belongs with and only with the owners of those tools; we assert an inherent right to decide for ourselves what software will and won't run, and when, on computers we own and operate for our own private benefit, and the same right held collectively over shared computers.
Further, we assert the right to revoke our consent to be used as a resource by the advertising and surveillance industries, as well as any other party not named specifically.
We therefore resolve to create, under common purpose and shared ownership, a new standard for a computing device, which is designed to educate and empower the owner, rather than to expose and exploit them.
I like where you're going with this. We need a new personal computer revolution that stays personal and accessible.
Once the corpos took control of the PC revolution they steered it in the direction they wanted. The new revolution needs more people like Woz and his open designs and less people like Steve Jobs and Epstein's good friends like Bill Gates.
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Then again, there is an excellent cross-compiler for the 65816 arch (Calypsi), which might make developing an OS easier.
All of this is moot, of course, if there turns out to be a better option for CPU.
Let us make a temporary, for-the-sake-of-argument example of what standards might look like:
Level 0:
- Z80 CPU at 18MHz or faster
- VT-100 terminal or compatible emulation
- ROMWBW HBIOS/CBIOS Support
- CP/M-3So level 0 is intentionally very broad, and essentially a reification of several existing systems.
Level 1:
- All requirements for Level 0
- 512KB of RAM
- Hardware designed according to the level 1 guidelines (replacing RC2014 or the like)Level 2:
- All requirements for levels 0 and 1
- CP/M-3 replaced with custom community-built OS (think MSX-DOS but with long file names). -
Let us make a temporary, for-the-sake-of-argument example of what standards might look like:
Level 0:
- Z80 CPU at 18MHz or faster
- VT-100 terminal or compatible emulation
- ROMWBW HBIOS/CBIOS Support
- CP/M-3So level 0 is intentionally very broad, and essentially a reification of several existing systems.
Level 1:
- All requirements for Level 0
- 512KB of RAM
- Hardware designed according to the level 1 guidelines (replacing RC2014 or the like)Level 2:
- All requirements for levels 0 and 1
- CP/M-3 replaced with custom community-built OS (think MSX-DOS but with long file names).@mos_8502 I wonder how hard it would be to port UXN to a system like that.
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Let us make a temporary, for-the-sake-of-argument example of what standards might look like:
Level 0:
- Z80 CPU at 18MHz or faster
- VT-100 terminal or compatible emulation
- ROMWBW HBIOS/CBIOS Support
- CP/M-3So level 0 is intentionally very broad, and essentially a reification of several existing systems.
Level 1:
- All requirements for Level 0
- 512KB of RAM
- Hardware designed according to the level 1 guidelines (replacing RC2014 or the like)Level 2:
- All requirements for levels 0 and 1
- CP/M-3 replaced with custom community-built OS (think MSX-DOS but with long file names).The level 1 hardware standards would be designed to use as much common, off-the-shelf hardware as possible, to make it easier to build a compliant system.
Imagine, for example, an RCBus system that fit into an ATX case and power supply?
